Isn't it all too good to be true?
Metamorphosis
Is it too good to be true? STARC says it's for real
Is that Joe Costello in those red pants? Oasys at DAC
DAC so far
Rock star T-shirt signing
How did Oasys get started?
Ten rules for corporate blog like this one
Harry the ASIC guy says "plausible"
Jay Singh, Plato Networks
Sanjiv Kaul on why he's involved with Oasys
Genomes
Renesas
Aggregation of silicon
Binary Decision Diagrams
Chip Design and the lyrics of the video
The new release
Bryon Moyer comes to visit
Cooley's DAC report is finally out
SCDsource article on Chip Synthesis
Welcome 2010
Gabe Moretti over at EDAcafe
EDA DesignLine
Innovation of the year: go and vote
Mystery fan on ESNUG
Sanjiv's opinion piece over at EEtimes
Gabe Moretti takes another look
Oasys a "must see" at DAC
The Documentation Challenge
Oasys is on Twitter
Sanjiv on "Ode to the Chip Synthesis Hero"
DAC
Gary Smith
Juniper Networks picks Oasys RealTime Designer
Gabe on EDA recommends seeing Oasys
Xilinx licenses Oasys Chip Synthesis technology
DAC in hindsight
Using High Level Synthesis and Chip Synthesis together
Cooley's Deepchip highlights Oasys DAC videos
The Entrepreneurial Engineer
Defining Chip Synthesis
Coolley's DAC report
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Oasys a "must see" at DAC 
Apr 30th, 2010 
Rather like suddenly finding Christmas merchandise in the stores in September, Bill Murray over at SCDsource has come out with his list of what to see at DAC. Wait, isn't DAC 6 weeks away? Has everything already been announced? And just a top 9 list, isn't 10 the traditional number?

Anyway, happily, Oasys RealTime Designer is on the list, the only synthesis tool to make the cut. Forte and Mentor are there for high-level synthesis but that is a completely different segment, starting from C/SystemC and delivering RTL, just ready to pour straight into RealTime Designer to get an implementation.

Here's Bill's description: Courtesy of Oasys, RealTime Designer is the biggest advance in logic synthesis in more than a decade. According to the company, it has the capacity to handle full-chip designs of up to 100 million gates; it is 20 to 100 times faster than mainstream synthesis tools, with better area and timing QoR. How? It operates and optimizes at the chip/RTL level – not merely the block/gate optimization level. A must see.
Posted By paulm at 5:56 pm CDT 
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