Isn't it all too good to be true?
Metamorphosis
Is it too good to be true? STARC says it's for real
Is that Joe Costello in those red pants? Oasys at DAC
DAC so far
Rock star T-shirt signing
How did Oasys get started?
Ten rules for corporate blog like this one
Harry the ASIC guy says "plausible"
Jay Singh, Plato Networks
Sanjiv Kaul on why he's involved with Oasys
Genomes
Renesas
Aggregation of silicon
Binary Decision Diagrams
Chip Design and the lyrics of the video
The new release
Bryon Moyer comes to visit
Cooley's DAC report is finally out
SCDsource article on Chip Synthesis
Welcome 2010
Gabe Moretti over at EDAcafe
EDA DesignLine
Innovation of the year: go and vote
Mystery fan on ESNUG
Sanjiv's opinion piece over at EEtimes
Gabe Moretti takes another look
Oasys a "must see" at DAC
The Documentation Challenge
Oasys is on Twitter
Sanjiv on "Ode to the Chip Synthesis Hero"
DAC
Gary Smith
Juniper Networks picks Oasys RealTime Designer
Gabe on EDA recommends seeing Oasys
Xilinx licenses Oasys Chip Synthesis technology
DAC in hindsight
Using High Level Synthesis and Chip Synthesis together
Cooley's Deepchip highlights Oasys DAC videos
The Entrepreneurial Engineer
Defining Chip Synthesis
Coolley's DAC report
Blog : View
Mystery fan on ESNUG 
Mar 12th, 2010 
The latest ESNUG newsletter contains an entry by an anonymous user from an anonymous company with high praise for RealTime Designer. They had run out of steam with DC getting big blocks synthesized, got up and running within a couple of hours and compiled their largest 5.8M instance block in 70 minutes in less than 2G of memory. You have to like the closing sentence though:
              "Overall I think Oasys has strong potential to replace Design Compiler."

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