One of the challenges with design flows involving high-level synthesis from C, C++ or SystemC is that eventually the exact performance of the design needs to be determined. The built-in metrics in HLS tools are fairly good at determining which of two implementation choices has the highest performance or consumes the least power and can thus guide the exploration of the design space.

However, sooner or later the actual performance or power numbers are required. If a design is to process 30 frames of high-definition video per second then 29 just doesn’t do it. And probably 50 frames per second would be wasting a lot of power and silicon area.

Traditional synthesis followed by placement is a cumbersome way of getting at this data. Chip Synthesis using Oasys RealTime Designer is much smoother, getting to a fully-placed design with accurate performance numbers in a short time. HLS can produce a lot of RTL, tens of thousands of lines, very quickly. Luckily RealTime Designer can easily process this fast to get the data that the system level designer needs to finalize a choice of implementation.

Paul van Besouw from Oasys and Devadas Varma of AutoESL have jointly written an article for Embedded Computing Design on just this topic.

Once again DAC has come and gone. Oasys’s DAC presence was in two parts: inside the suites and the video wall.

Inside the suites the show was almost fully booked. Gary Smith had recommended Oasys on his DAC must-see list (and, organized in order of booth number, fortuitously came at the top of the list). In his Monday morning DAC presentation he talked about Oasys as appearing to be a “real game changer,” which obviously further helped drive up interest and bring decision makers to see the demos. There were two demos, the “normal” one about Chip Synthesis and RealTime Designer’s basic capabilities of synthesizing to placed gates in extraordinarily fast run-times. And a second demo focused on power optimization where an entire design is resynthesized after the voltage of one of its power domains is reduced (so that the unchanged netlist misses timing).

On the video wall were half-a-dozen videos in the style of the “I’m a Mac, I’m a PC” ads comparing Oasys to Synopsys (no prizes for guessing which the cool young Mac-like guy was). With consolidation of DAC, Oasys’s booth had ended up being in one of the far corners, not as good a location as it had looked on the map when the location was picked. But the videos were their own draw. Synopsys execs, even Aart, would walk by pretending not to look, or hold a conversation with Sanjiv while mainly looking over his shoulder. The videos manage to get the point of Oasys’s superior technology across while being humorous and in good taste. Click here or on the home page to watch the videos.

Also available as a giveaway for special customers, EDAgraffiti the book. Except that everyone forgot about them and they remained boxed up for the whole of DAC. Oh well, remaindered already.

Oasys today announced that it has closed a deal with Juniper Networks. This is significant for a number of reasons.

Firstly, Juniper designs incredibly complex chips with aggressive performance, since as much as anything their ability to do so is what differentiates them from their competition. Because RealTime Designer can handle Juniper’s designs means it can handle pretty much the most challenging designs in the industry.

Secondly, Juniper has historically been a Synopsys house using Synopsys for both synthesis and place and route. Winning a benchmark in that kind of environment is significant. As Debashis Basu, the VP of Silicon Development at Juniper says, “It’s a great tool that fits a very real performance need.”

Thirdly, Juniper have gone public on their adoption of RealTime Designer and so are a reference account, rather than keeping their heads down to avoid any potential bad feeling with their primary tool supplier, Synopsys.

I couldn't put it better myself. Winning in a high-profile account like Juniper Networks is a great achievement for the Oasys team.

DAC is coming up in just a few weeks, of course. Oasys will be there at booth 202. Following on from last year’s rock video, Oasys will have something new this year…but you’ll have to come by and see it for yourself, my lips are sealed.

If you are interested in a suite demo, then you can signup. Go to the home page and click on either the DAC logo or the big red “register” logo. That will take you to a page where you can request a slot. Further, one person each day who attends a suite demo will win an Apple iPad.

SCDsource has already called Oasys a "must-see" at this year's DAC. So sign up and make sure you don't miss it.

              "Overall I think Oasys has strong potential to replace Design Compiler."

There is a new piece up on EDA DesignLine (I think that’s how they write it, with a space after EDA but not after Design; when was it that companies started to write their names like variables in a C program?).

The article is in the usual house style of the websites that grew out of print where you are meant to maintain the fiction that, despite being written by the CEO of Oasys, the piece is just an survey of the industry and doesn’t mention the company by name.

It’s rather off-topic, but there is an interesting article by Michael Kinsely in The Atlantic Monthly about similar obsolete rules in journalism, where the journalist isn’t allowed to critique any statement by someone being interviewed. Instead, to be “objective,” the journalist has to find someone who has that opinion and present them as taking the contrary position, despite the fact that you may well never have heard of the person. Worse, the fact that the journalist works for a brand name newspaper or magazine may be the only reason to take the article more seriously than something by a blogger. But when things get technical, the bloggers tend to know their subjects much better than the supposedly more professional bloggers

Actually I overstated the case about product names. You are allowed one mention so both Oasys and RealTime Designer (I think I got the spaces right again there; when was it that product names...) slip into the final sentence, if you read that far.

And you should. I think that this is the best piece Oasys has written explaining how RealTime Designer works and highlighting just how dramatically different its results are compared with the usual synthesis suspects.

Share it with all your friends. Less fun that skateboarding dogs but more relevant if you are designing large chips and assembling  the hundreds of jigsaw pieces of your chip into something that gets close to the picture on the box that marketing gave you.